OUTMODE=OUTMODE_0, PCS=PCS_0, ONCE=ONCE_0, SCS=SCS_0, LENGTH=LENGTH_0, DIR=DIR_0, COINIT=COINIT_0, CM=CM_0
Timer Channel Control Register
| OUTMODE | Output Mode 0 (OUTMODE_0): Asserted while counter is active 1 (OUTMODE_1): Clear OFLAG output on successful compare 2 (OUTMODE_2): Set OFLAG output on successful compare 3 (OUTMODE_3): Toggle OFLAG output on successful compare 4 (OUTMODE_4): Toggle OFLAG output using alternating compare registers 5 (OUTMODE_5): Set on compare, cleared on secondary source input edge 6 (OUTMODE_6): Set on compare, cleared on counter rollover 7 (OUTMODE_7): Enable gated clock output while counter is active |
| COINIT | Co-Channel Initialization 0 (COINIT_0): Co-channel counter/timers cannot force a re-initialization of this counter/timer 1 (COINIT_1): Co-channel counter/timers may force a re-initialization of this counter/timer |
| DIR | Count Direction 0 (DIR_0): Count up. 1 (DIR_1): Count down. |
| LENGTH | Count Length 0 (LENGTH_0): Count until roll over at $FFFF and continue from $0000. 1 (LENGTH_1): Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. |
| ONCE | Count Once 0 (ONCE_0): Count repeatedly. 1 (ONCE_1): Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. |
| SCS | Secondary Count Source 0 (SCS_0): Counter 0 input pin 1 (SCS_1): Counter 1 input pin 2 (SCS_2): Counter 2 input pin 3 (SCS_3): Counter 3 input pin |
| PCS | Primary Count Source 0 (PCS_0): Counter 0 input pin 1 (PCS_1): Counter 1 input pin 2 (PCS_2): Counter 2 input pin 3 (PCS_3): Counter 3 input pin 4 (PCS_4): Counter 0 output 5 (PCS_5): Counter 1 output 6 (PCS_6): Counter 2 output 7 (PCS_7): Counter 3 output 8 (PCS_8): IP bus clock divide by 1 prescaler 9 (PCS_9): IP bus clock divide by 2 prescaler 10 (PCS_10): IP bus clock divide by 4 prescaler 11 (PCS_11): IP bus clock divide by 8 prescaler 12 (PCS_12): IP bus clock divide by 16 prescaler 13 (PCS_13): IP bus clock divide by 32 prescaler 14 (PCS_14): IP bus clock divide by 64 prescaler 15 (PCS_15): IP bus clock divide by 128 prescaler |
| CM | Count Mode 0 (CM_0): No operation 1 (CM_1): Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 2 (CM_2): Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 3 (CM_3): Count rising edges of primary source while secondary input high active 4 (CM_4): Quadrature count mode, uses primary and secondary sources 5 (CM_5): Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 6 (CM_6): Edge of secondary source triggers primary count until compare 7 (CM_7): Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. |